1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a floating gate in which a charge corresponding to data is stored.
Nowadays, EPROM devices, EEPROMs and flash memory devices are known as non-volatile semiconductor memory devices. The non-volatile semiconductor memory devices has a structure in which a charge is injected into a floating gate of a memory cell and is drawn therefrom. Hence, data can be written into and read from the memory cell.
2. Description of the Related Art
A conventional non-volatile semiconductor memory device will be described with reference to FIG. 1, which shows a circuit configuration thereof directed to a data read operation. The circuit shown in FIG. 1 includes a memory cell array 101 having memory cell transistors 107, an address buffer 102, a word line (WL) decoder 103, a bit line (BL) decoder 104, a sense amplifier 105, and an output buffer 106. The address buffer 102 temporarily stores an address signal. The word line decoder 103 decodes the address and thus generates a voltage applied to the control gates of the memory cell transistors 107. The bit line decoder 104 decodes the address and thus generates a voltage applied to the drains of the memory cell transistors 107. The sense amplifier 105 includes sense amplifier circuits respectively provided for the bit lines. Each of the circuits compares a bit line current flowing in the corresponding memory cell transistor 107 with a predetermined reference current, and senses data stored in the memory cell. The output buffer outputs data. The sources of the memory cell transistors 107 are grounded.
The data stored in each memory cell transistor 107 depends on the presence/absence of a charge in the floating gate. When the memory cell transistor 107 stores data "0", the floating gate is charge with negative electricity due to the electrons charged therein. Even when voltages for the read operation are applied to the control gate and drain of the memory cell transistor 107, the drain current little flows because the threshold voltage is increased.
When data "1" is stored in the memory cell transistor 107, little electrons are present in the floating gate. Hence, the transistor 107 has a decreased threshold voltage and the drain current flows when voltages for the read operation are applied to the control gate and drain.
The data read operation of the device shown in FIG. 1 is carried out as follows by utilizing the above operation of the memory cell transistor 107.
When an address is applied to the address buffer 102, the word line decoder 103 selects one of the word lines, and the bit line decoder 104 selects one of the bit lines. Hence, one memory cell transistor 107 connected by the selected word line and bit line is selected. When the voltages are applied to the control gate and drain of the selected memory cell transistor 107, the drain current flows in the bit line. At that time, some memory cell transistors are connected to the selected bit line in which the above drain current flows. However, these memory cell transistors are not selected because the corresponding word lines are not selected. Hence, ideally, the bit line current consists of only the drain current of the selected transistor 107, and is not affected by the memory cell transistors 107 connected to the same bit line as the selected transistor 107.
The sense amplifier 105 compares the bit line current flowing in the bit line to which the selected cell is connected with the reference current, and thus determines whether data "0" or data "1" is stored in the memory cell transistor 107. As shown in FIG. 2, the reference current is proportional to the voltage applied to the control gate. The sense amplifier 105 compares the bit line current of the memory cell transistor 107 obtained when the voltage of a read level is applied to the control gate with the reference current. When the bit line current is greater than the reference current, the sense amplifier 105 senses "1". When the bit line current is less than the reference current, sense amplifier 105 senses "0". The output buffer 106 outputs data based on the sensed result from the sense amplifier 105.
It is required to determine the reference current taking into account an over erase effect of the memory cells having the floating gates. In the case where data is read from a selected memory cell 107, if there is an over-erased cell connected to the bit line to which the selected cell is connected, a drain current will flow in the over-erased cell although the over-erased cell is not selected. Of course, no drain currents flow in all the other normal, non-selected cells connected to the selected bit line. Hence, the current flowing in the bit line to which the selected memory cell transistor 107 is connected includes not only the drain current of the selected transistor 107 but also the drain currents of the over-erased transistors. Hence, as indicated by solid arrows in FIG. 3, an increased amount of the current flows in the bit line, and greatly deviates from the original level illustrated by a broken line, irrespective of whether the selected memory cell transistor 107 stores "1" or "0".
With the above in mind, the amount of the reference current is selected so that it is not equal to half the difference between the drain current for "1" and the drain current for "0" but is closer to the drain current for "1", as shown in FIG. 2.
However, the above setting of the reference current will be affected by a charge gain effect in which the number of electrons in the floating gate increases with elapse of time. Due to the charge gain effect, there is a possibility that the sense amplifier 105 may mistakenly read data stored in the selected memory cell transistor 107 so that it reads "0" although "1" is actually stored.
In order to improve the reliability of the non-volatile semiconductor memory devices, a particular arrangement is employed. For example, as shown in FIG. 4, the memory cell array 101 is segmented in memory cell arrays 101a, 101b and 101c. A majority decision circuit 108 receives data read from the arrays 101a, 101b and 101c. The memory cell arrays 101a, 101b and 101c have an identical address area and store identical data. The output data of the majority decision circuit 108 is the output data of the non-volatile semiconductor memory device.
FIG. 5 shows the truth table of the majority decision circuit 108. As shown in FIG. 5, the majority decision circuit 108 outputs "0" when the output signals of the memory cell arrays 101a, 101b and 101c are any of "000", "001", "101" and "100", and outputs "1" when the outputs are "011", "101", "110" and "111". Hence, even if the read data from one of the memory cell arrays 101a, 101b and 101c happens to be changed, the erroneous data is finally corrected and output by the majority decision circuit 108. Hence, the reliability of the device can be improved. As an increased number of segmented memory cell arrays is employed, more improved reliability can be obtained.
However, as the reliability of the device is improved, an increased number of segmented arrays occupy an increased area on the chip.